Author Topic: 3.5 GHZ (Read 1081 times)

BOOT · « **Reply #30 on:** September 28, 2001, 05:09:00 PM »

Did I stumble into a foreign country here ???

Geez I wish I understood what you guys are talking about...

Makes my head spin...

BOOT

bloom25 · « **Reply #31 on:** September 28, 2001, 05:43:00 PM »

If you think your head is spinning, you should try sitting through some of the classes I'm taking this term.

I usually end up with a migraine at the end of them.

I've done some more research into GaAs since the Motorola announcement a month ago. One problem they did not mention is that heat is harder to dissipate off GaAs than Si. There are some advantages to GaAs that tend to improve the situation. GaAs has an intrinsic carrier concentration of about 2.25x10^6/cm^3 as opposed to Si with 1x10^10/cm^3 (at 300K), meaning it's easier to control. This gets even better as temperature increases, at 400K silicon is up to around 8x10^12/cm^3 and GaAs is only 8x10^9, which is better than Si at room temperature. This kind of nullifies the issue that GaAs is harder to remove heat from, though as clock speeds ramp up I still see heat as a very big issue though. The advantages of GaAs over silicon are enormous when it comes to clock speed that can be attained. Even at light doping levels the electron mobility in GaAs is MUCH higher than Si, due to the elecrons much reduced effective mass. My pocket reference book tells me 1360cm^2/V-sec for n-type doped at 10^14/cm^3 in Si VERSUS 8000cm^2/V-sec with equal doping in GaAs, both at room temp. That means that the electrons are moving 6 TIMES faster in GaAs than Si under fairly equal conditions. That means that if Intel could use GaAs right now with the P4 design 10Ghz would probably be attainable today.

At this point I think Gordon Moore's statement will probably hold true for another 18 months, after that we'll just have to wait and see what happens.

Once we do find out how to use GaAs (or SiC) we can expect clock speeds to take off once again.

(DejaVu, I was wondering how many Angstroms thick and the K' values for the dielectrics you were working with are? If it's not a trade secret that is... I'm just curious to do some spice simulation runs to see what's possible.

)

Vermillion · « **Reply #32 on:** September 28, 2001, 07:05:00 PM »

Another EE here

Graduated Dec. 91 from WVU, mostly specializing digital control systems, and anything to do with computer systems/applications

I then by a blind fluke of fate ended up going to grad school, and getting my Masters in Environmental Engineering from Marshall University. Yah I know strange combo, but its a long story.

I now do Environmental/Pollution Computer Simulations for the government. Its actually quite fun

I get to play with some REALLY big computer systems. Trying to talk my boss into building a nice 16 node Beowulf cluster right now.

I never really was into chip design, but I'm glad I still at least understand the technology/terminology that you guys are discussing, so I'm not too far out of the loop.

Cya at the Con !

Sorrow[S=A] · « **Reply #33 on:** September 28, 2001, 09:22:00 PM »

Moore allready adjusted his law.

There are now clauses and rules for it. I can't remember all of them but a search on the web should show it.

AKDejaVu · « **Reply #34 on:** September 29, 2001, 11:31:00 AM »

Quote

That means that if Intel could use GaAs right now with the P4 design 10Ghz would probably be attainable today.

Sorry bloom... that's just not true. You are focussing too much on one aspect and not really figuring in the rest. Each processor is basically two sections.. the top end (metal lines and interconnects) and the transistors. In one area, we'd see a definate improvement... enough to totally melt the other area.

The 3.6GHz is going to be achieved on bare Si. I do know that GaAs and SOI are being looked at, but the cost per unit involved with each goes up dramatically... especially on 12" wafers. I'm not sure if much GaAs processing is going on above 6" right now. Triquent is one of the main movers in this area and they are still on 4" wafers.

Quote

At this point I think Gordon Moore's statement will probably hold true for another 18 months, after that we'll just have to wait and see what happens. Once we do find out how to use GaAs (or SiC) we can expect clock speeds to take off once again.

LOL! People have been saying that about Moore's law for 15 years now

Its our job to keep proving Dr. Moore right... and we do it well

And I don't necesserily know that your two options for improving speed are really the only path. I do believe that after 10GHz, we'll have to go in a completely different direction... but I'm pretty sure nobody has any idea what that is right now. We have several things we're looking at, but the above are only two of them... there are many more other options to explore.

Quote

DejaVu, I was wondering how many Angstroms thick and the K' values for the dielectrics you were working with are? If it's not a trade secret that is... I'm just curious to do some spice simulation runs to see what's possible.

The current process of record (data is published) runs the ILD <inter layer dielectric> anywhere from 1.2um to 3um with an effective K value somewhere around 3.6. I can't really say what K value we're working on for future processes... but it considerably less than the above mentioned.

Besides.. in addition to the k and thickness, you'd have to know the line pitch and via height. Remember, with copper we use a dual damazine process where we etch the vias, then we etch trenches and fill the whole thing in with copper. That means the ILD thickness is the height of one whole via/metal layer as opposed to being the distance between two metal layers.

AKDejaVu

Zigrat · « **Reply #35 on:** September 29, 2001, 02:33:00 PM »

double e dorks. real engineers build airplanes

bloom25 · « **Reply #36 on:** September 29, 2001, 03:40:00 PM »

You're right, I forgot totally about the interconnects and such.

(I work mainly with design, not layout so that stuff really doesn't enter my mind.

)

3.6 is the the Er value for regular old silicon so that doesn't surprise me much.

Oh, and Zigrat, you are totally wrong. REAL engineers build egos.

Mini D · « **Reply #37 on:** February 03, 2003, 11:58:44 AM »

Quote

Originally posted by AKDejaVu
As for AMD and SOI on a .13 micron process... I'd venture to say you'll see them do .13 micron long before you see it on SOI.

Hehehehe... anyone read the news on this today?

MiniD

Wlfgng · « **Reply #38 on:** February 03, 2003, 12:02:55 PM »

Quote

REAL engineers build egos.

and all this time I thought they only built cube-farms...

bloom25 · « **Reply #39 on:** February 03, 2003, 09:39:09 PM »

LOL, who dug this up? This is like going back in time to when tech companies made money!

Judging by what was posted above it looks like we did alright in our predictions. The Barton core Athlon XPs come out on the 10th of this month in the 2500+ and 3000+ speeds. They aren't using SOI technology though. I think Opteron (Hammer) will be the first AMD cpu to do that, and it's supposed to be out in April. I think Intel is supposed to launch the 3.2GHz P4 in March or April as well.

Mini D · « **Reply #40 on:** February 03, 2003, 11:19:51 PM »

A tidbit on SOI:

http://biz.yahoo.com/rc/030131/tech_amd_athlon_1.html

bloom25 · « **Reply #41 on:** February 04, 2003, 01:22:13 AM »

I read that the other day. It didn't surprise me too much really. There doesn't seem to be a whole lot going as far as CPU releases until the second half of this year. From a practical standpoint, I can see why AMD would do this.

The way I see it, Athlon 64 and Opteron (Hammer) are a make or break type product for AMD. Considering the fact Hammer CPUs are built on a more expensive partially depleted channel SOI wafer, have a considerably larger die size, and increased packaging costs (750+ pin chip), it makes some sense that AMD would want to push the existing Tbred 'B' and Barton cores to their limits. (About 2.5 GHz true clock speed.)

I also can't think of much of a reason to push 64 bit on the consumer market. The reality of the situation is that there are very few circumstances where a 64 bit processor would be required by most home users. (Very large data sets or extremely high precision mathematical computations.) Obviously it's worth some marketing value, but probably not much real practical value until software is written that can take advantage of it. (It's also worth considering that the mcuh greater number of gates required for a 64 bit ALU and FPU and the associated larger registers required by them will also increase die size and thus costs.) Since Opteron is targeted toward the workstation/server market, it makes sense to launch it sooner.

Hammer does have some performance enhancing features though. It adds SSE2 instruction support, which will certainly allow it to benefit greatly in applications now optimized for the P4. Its on die memory controller will also increase performance by reducing memory latency. (It also reduces MB chipset northbridge costs significantly.) Since Opteron is supposed to launch at 1.4, 1.6, and 1.8 GHz true clockspeeds and a rating somewhere around that of a 3.2 GHz P4 for the 1.8 GHz model it appears AMD will match the performance of the Intel Xeon processors available in that time frame.

Mini D · « **Reply #42 on:** February 04, 2003, 12:52:06 PM »

I wasn't as much reffering to the delay as to the cause of the delay. IBM went through a series of miraculous process disclosures. Low-K spin-on dielectric and SOI being two thrown out in the mix. Since then, they've already dropped the Low-K dielectric due to integration issues. I'm wondering if the SOI will go next due to scaling issues.

MiniD

bockko · « **Reply #43 on:** February 04, 2003, 01:23:39 PM »

3 GHz will be pretty easy... beyond that we're not sure exactly what we are going to do.

AKDejaVu
Intel - Components Research
________________________

watch what you say when you say it

only the paranoid survive..

regards,
andy and craig

Skuzzy · « **Reply #44 on:** February 04, 2003, 01:35:52 PM »

Isn't Intel doing some 90nm runs this year?