my current mobo is QPI based. X58
Has this changed much or are the ram and cpu clock speeds still intertwined?
This was a limitation on OC'ing my X58 system. I have 2000MHz ram installed but in order to get what works with a 4GHz cpu OC its DC'ed to 1668MHz with turbo timings. I noticed that ram speeds are now at 3440MHz and crap. So how are the cpu and DDr4 ram playing together?
Pudgie my head hurts man. 
NAS is cool. I got a 1TB WD MyBook. Separate unit that has ethernet port to router.
BD, I had read what your talking about regarding core count and bclk. I think the link, earlier post, for OC'ing broadwell hits on this. Good info ty.
Sorry for that MADe, hope it hurts in a good way.................
Intel X58 mobo block diagram was a direct copy of the AMD mobo block diagram (can't remember the chipset name) that the AMD Athlon\Phenom CPU's used (which is the current block diagram being used on all current AMD mobos today) w\ different naming for the exact same tracing. This was part of the licensing agreement between AMD and Intel when Intel licensed the rights to use the AMD Athlon CPU architecture (which brought about the Intel Nehalem CPU and X58 chipset). The limiting part was the Northbridge chipset\QPI link as this chipset\link had to handle the entire data stream of the mobo so these parts were very sensitive when pushed to capacity, especially when OC'ing (if mem serves me here, to OC the CPU you also had to work the QPI setup along w\ the mem as all this had to match up on clock timings and speed\bandwidth limited by power available, correct?).
Intel solved all this starting w\ X79 and Z68 when the Northbridge chipset was essentially eliminated (all this circuitry moved to the CPU die along w\ the DMA controller and all tracing) and all is now clocked at the on-die CPU core clock speed on very short tracing incorporating an L3 cache on the CPU side w\ the DMA controllers interfacing between the CPU cores\L3 cache, system mem, dedicated PCI-E lanes (graphics cards) and the Southbridge chipset thru QPI\DMI serial links so in effect they do not actually "talk or are intertwined" directly to each other anymore, but to each other thru the on-die DMA controllers w\ the DMA controllers handling the interrupt switching between CPU, graphics card(s) and Southbridge chipset to system mem cache. The development of these very sophisticated DMA controllers are a big part of Intel's overall dominance over AMD since SandyBridge and IMHO is the main reason why Intel hasn't really pushed CPU core clock speeds much on their HEDT\mainstream setups and concentrated more on core counts to improve overall system thruput and reduce power usage at the same time by reducing CPU clock speed when feasible while retaining good single threaded performance (gaming importance) and why these Intel packages since Z68\X79 demonstrate very little to no overall gaming performance drop off as well across platform upgrades.
I also suspect that AMD w\ Zen is going to reverse license w\ Intel due to the existing licensing agreement between them to incorporate a similar copy of Intel's current version of the HEDT block diagram (x99) as this is now a somewhat "pedestrian" diagram to conclude this license. My hunch on this only as this makes the most sense for AMD to do.
Time will tell.
