Yes, I meant gate length...
(I'm pretty bad at reading over my posts to make sure I didn't mess up something simple.
) I hate to admit it, but most of my knowledge is based on work with a .5um (HP) and .35um (TSMC) process, so I'm not totally clued in on particular issues dealing with newer processes. With these two processes, the .5 um, for example, refered to the minimum gate length, and the minimum spacing between contacts and metal layers was .25 um (if I remember right). You don't really have to worry about it, because when you run DRC (design rule check) it will tell you if you violated any design rules for that particular process.
Beet1e, most of the stuff I've learned has been through CPU architecture classes, digital logic design classes (most of my interests are in ASIC design which are coded in VHDL, but many of the concepts hold true for both CPUs and Asics), and a LOT of personal interest in the area that give me the drive to actually attempt to "read" books on the subject. I've also done some work with various microcontrollers (Intel 8051/8031, PICs, etc). (Trust me, engineering books are neither easy to read and really aren't the slightest amount of fun either... )
If you want a general overview at a slightly higher level than what I posted above, I think there are some good articles at
http://www.arstechnica.com . (Animal posted a link to that site, and I think there were some articles there about the K7 (Athlon) core. I don't know how accurate it is, but from the few articles I looked at it looked pretty good.)
Most of the design I do (unless it's very basic) is actually done via a programming language called VHDL. This language is similar to C in structure, and is very easy to read if you have any knowledge in programming. It allows you to define "components" which are somewhat similar to objects in other programming languages (Java comes to mind). It allows you to remove yourself to some degree from the actual hardware and focus more on behavioral aspects. For example, given the correct library for the type of logic gates you are using, you can just type: a <= vector1 + vector2; and when this code is compiled and synthesized you will actually get an adder (what type depends on whether you wanted it optimized for speed or area). You can do structural coding as well, and the synthesis tool will make a number of optimizations for you if you code it correctly. (And gates replaced with Nand gates, ors with nors, etc)
This language was developed for the DoD and the first version became available in 1987 (VHDL '87), it was revised in 1993. There is some current work to extend it to analog circuits as well. Nearly ALL Asic (application specific integrated circuits) designs are now done to some degree using VHDL or Verilog (similar to VHDL, but not as good IMO).